1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor design, and more particularly, to an internal voltage generation circuit of a semiconductor device.
2. Description of the Related Art
In general, semiconductor memory devices, including Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) devices, include an internal voltage generation circuit for efficient power consumption and internally generate and use internal voltages with various voltage levels. Internal voltages include a core voltage, having a voltage level between an external power source voltage and a ground power source voltage, and a peripheral voltage. Additionally, there is a pumping voltage, having a higher voltage level than the external power source voltage, and a substrate bias voltage, having a lower voltage level than the ground power source voltage. The pumping voltage is conventionally generated from a charge pumping operation.
FIG. 1 is a block diagram illustrating a first pumping voltage generation circuit according to prior art.
Referring to FIG. 1, the first pumping voltage generation circuit 100 includes a voltage level detector 110, a reference oscillation signal generator 120, an oscillation signal generator 130, and a pumping voltage generator 140. The voltage level detector 110 receives a reference voltage VREF and detects a pumping voltage VPP. The reference oscillation signal generator 120 generates a reference oscillation signal OSCP_PRE in response to a detection signal VPPOSCEN outputted from the voltage level detector 110. The oscillation signal generator 130 sequentially generates a plurality of oscillation signals OSC1 to OSC6 in response to the reference oscillation signal OSCP_PRE. The pumping voltage generator 140 generates the pumping voltage VPP in response to the oscillation signals OSC1 to OSC6.
Herein, the voltage level detector 110 is an element for detecting the pumping voltage VPP consistently based on the reference voltage VREF, and the voltage level detector 110 also monitors whether the voltage level of the pumping voltage VPP is higher or lower than the reference voltage VREF continuously.
The reference oscillation signal generator 120 performs an oscillation operation when the voltage level of the pumping voltage VPP is lower than the reference voltage VREF. For example, when the voltage level of the pumping voltage VPP is lower than the reference voltage VREF, the detection signal VPPOSCEN may be enabled thereby triggering the reference oscillation signal generator to perform an oscillation operation. In performing an oscillation operation, the reference oscillation signal generator 120 generates the reference oscillation signal OSCP_PRE having a predetermined frequency. Meanwhile, the reference oscillation signal generator 120 generates an initialization signal OSCP_RST in response to the detection signal VPPOSCEN and applies the initialization signal OSCP_RST to the oscillation signal generator 130.
Next, the oscillation signal generator 130 generates the oscillation signals OSC1 to OSC6, having a predetermined phase difference from each other, by dividing and shifting the frequency of the reference oscillation signal OSCP_PRE. Herein, the oscillation signals OSC1 to OSC6 are sequentially oscillated due to the predetermined phase difference. Further, the oscillation signal generator 130 is initialized in response to the initialization signal OSCP_RST.
Also, the pumping voltage generator 140, although not illustrated in the drawing in detail, includes a plurality of pumping voltage units. Each of the pumping voltage units receives one corresponding oscillation signal from among the oscillation signals OSC1 to OSC6 and sequentially performs a charge pumping operation.
Hereafter, the operation of the first pumping voltage generation circuit 100 having the above-described structure is described.
In this specification, for the sake of convenience in description, a case where the voltage level of the pumping voltage VPP is lower than the voltage level of the reference voltage VREF is referred to as an active mode, while a case where the voltage level of the pumping voltage VPP is higher than the voltage level of the reference voltage VREF is referred to as a pre-charge mode.
First, the active mode is described,
The voltage level detector 110 enables the detection signal VPPOSCEN when the voltage level of the pumping voltage VPP is lower than the reference voltage VREF. For example, the voltage level detector 110 outputs a detection signal VPPOSCEN of a logic high level.
The reference oscillation signal generator 120 then performs an oscillation operation in response to the detection signal VPPOSCEN and enables the reference oscillation signal OSCP_PRE. The oscillation signal generator 130 sequentially enables the oscillation signals OSC1 to OSC6 in response to the reference oscillation signal OSCP_PRE. In other words, the oscillation signal generator 130 outputs the oscillation signals OSC1 to OSC6 having the predetermined phase difference by dividing and shifting the frequency of the reference oscillation signal OSCP_PRE.
Accordingly, the pumping voltage generator 140 sequentially performs a charge-pumping operation in response to the oscillation signals OSC1 to OSC6 that are sequentially enabled so as to generate the pumping voltage VPP.
Second, the pre-charge mode is described.
When the voltage level of the pumping voltage VPP becomes higher than the reference voltage VREF, the voltage level detector 110 disables the detection signal VPPOSCEN. For example, the voltage level detector 110 outputs a detection signal VPPOSCEN of a logic low level.
Accordingly, the reference oscillation signal generator 120 and the oscillation signal generator 130 stop the oscillation operation, thereby causing the pumping voltage generator 140 to stop the charge pumping operation.
The first pumping voltage generation circuit 100 described above may minimize noise caused in the pumping voltage VPP by sequentially performing the charge pumping operation.
The first pumping voltage generation circuit 100, however, has the following drawbacks.
FIG. 2 is a timing diagram of the oscillation signals OSC1 to OSC6 for describing disadvantages of the first pumping voltage generation circuit 100. FIG. 2 illustrates an exemplary scenario in which the first pumping voltage generation circuit 100 enters an active mode ACT, subsequently switches to a pre-charge mode PCG, and then switches back to the active mode ACT.
Referring to FIG. 2, the oscillation signals OSC1 to OSC6 are toggled in the active mode and pre-charged to a certain voltage level (e.g., a predetermined voltage level) in the pre-charge mode. Herein, when the oscillation signals OSC1 to OSC6 are pre-charged to a logic high level, the oscillation signals OSC1 to OSC6 remain at the logic high level for one cycle 1tCK after the mode is switched into the active mode, which is problematic. This is because the oscillation signal generator 130 includes a frequency dividing unit (not shown). To be specific, the frequency dividing unit typically includes a T-flipflop, and the T-flipflop characteristically causes a delay of one cycle 1tCK.
To overcome the above problems, a second pumping voltage generation circuit, which controls the oscillation signals OSC1 to OSC6 to be pre-charged when the oscillation signals OSC1 to OSC6 are in a logic low level in the pre-charge mode, may be implemented.
FIG. 3 is a block diagram illustrating a second pumping voltage generation circuit according to additional prior art, and FIG. 4 is an internal circuit diagram illustrating a reference oscillation signal generator and an oscillation signal generator that are shown in FIG. 3.
Herein, for the sake of convenience in description, the same signal symbols and element names as those appearing in the first pumping voltage generation circuit 100 of FIG. 1 are used to describe the second pumping voltage generation circuit.
Herein, those structures of the second pumping voltage generation circuit which differ from those of the first pumping voltage generation circuit 100 shown in FIG. 1 are described.
Referring to FIG. 3, an oscillation signal generator 230 of the second pumping voltage generation circuit 200 applies a pre-charge signal OSCP_PCGENB, which is enabled in the pre-charge mode, to a reference oscillation signal generator 220. This is described in detail with reference to FIG. 4.
Referring to FIG. 4, the reference oscillation signal generator 220 generates a reference oscillation signal in response to a pre-charge signal OSCP_PCGENB and a detection signal VPPOSCEN. The oscillation signal generator 230 sequentially generates a plurality of oscillation signals OSC1 to OSC6 in response to a reference oscillation signal OSCP_PRE.
The oscillation signal generator 230 includes a frequency dividing/shifting unit 232, a sequential oscillation signal generation unit 234, and a pre-charge signal generation unit 236. The frequency dividing/shifting unit 232 generates first and second source oscillation signals OSC_ODD and OSC_EVEN in response to the reference oscillation signal OSCP_PRE. The sequential oscillation signal generation unit 234 sequentially generates the oscillation signals OSC1 to OSC6 in response to the first and second source oscillation signals OSC_ODD and OSC_EVEN. The pre-charge signal generation unit 236 generates the pre-charge signal OSCP_PCGENB in response to the first and second source oscillation signal OSC_ODD and OSC_EVEN.
The frequency dividing/shifting unit 232 generates the first source oscillation signal OSC_ODD by dividing the reference oscillation signal OSCP_PRE, and generates the second source oscillation signal OSC_EVEN by shifting the source oscillation signal OSC_ODD by a predetermined time.
The pre-charge signal generation unit 236 generates the oscillation signals OSC1 to OSC6 that are sequentially enabled in response to the first and second source oscillation signals OSC_ODD and OSC_EVEN.
The pre-charge signal generation unit 236 enables the pre-charge signal OSCP_PCGENB when the first and second source oscillation signals OSC_ODD and OSC_EVEN are both at a predetermined voltage level. For example, the pre-charge signal generation unit 236 outputs a pre-charge signal OSCP_PCGENB of a logic low level when the first and second source oscillation signals OSC_ODD and OSC_EVEN are both at a logic low level.
Hereafter, the operation of the second pumping voltage generation circuit 200 having the above-described structure is described with reference to FIG. 5. Herein, for the sake of convenience in description, the operations of the reference oscillation signal generator 220 and the oscillation signal generator 230 are described, and they are described in the order of an active mode ACT switched to a pre-charge mode PCG and then from the pre-charge mode PCG back to the active mode ACT.
FIG. 5 is a timing diagram of the oscillation signals OSC1 to OSC6.
Referring to FIG. 5, once the second pumping voltage generation circuit 200 enters the active mode ACT, the reference oscillation signal generator 220 toggles the reference oscillation signal OSCP_PRE in response to an enabled detection signal VPPOSCEN, and the oscillation signal generator 230 sequentially toggles the oscillation signals OSC1 to OSC6 in response to the toggling reference oscillation signal OSCP_PRE.
In this state, when the second pumping voltage generation circuit 200 is switched into the pre-charge mode PCG, the pre-charge signal generation unit 236 enables/outputs a pre-charge signal OSCP_PCGENB of a logic low level when the first and second source oscillation signals OSC_ODD and OSC_EVEN are both at a logic low level.
Then, the reference oscillation signal generator 220 generates the reference oscillation signal OSCP_PRE in response to the enabled pre-charge signal OSCP_PCGENB, and the oscillation signal generator 230 receives the generated reference oscillation signal OSCP_PRE and fixes and outputs the received reference oscillation signal OSCP_PRE when the oscillation signals OSC1 to OSC6 are at a logic low level. In short, when the pre-charge signal OSCP_PCGENB is enabled, the oscillation signals OSC1 to OSC6 are pre-charged when they are at a logic low level.
Subsequently, when the mode is switched back to the active mode ACT, as described earlier, a series of operations corresponding to the active mode ACT are performed, sequentially toggling the oscillation signals OSC1 to OSC6.
The second pumping voltage generation circuit 200 has an advantage of toggling the oscillation signals OSC1 to OSC6 without a delay in the next active mode by pre-charging the oscillation signals OSC1 to OSC6 to a predetermined voltage level in the pre-charge mode PCG.
The second pumping voltage generation circuit 200, however, has the following drawbacks.
FIGS. 6 and 7 illustrate concerns associated with the second pumping voltage generation circuit 200.
Referring to FIG. 6, the reference oscillation signal generator 220 and the oscillation signal generator 230 are disposed away from each other to decrease the signal line of the second pumping voltage generation circuit 200. In other words, three signal lines for transferring the reference oscillation signal OSCP_PRE, the initialization signal OSCP_RST, and the pre-charge signal OSCP_PCGENB, respectively, are disposed between the reference oscillation signal generator 220 and the oscillation signal generator 230. Since six signal lines for transferring the oscillation signals OSC1 to OSC6 are disposed between the oscillation signal generator 230 and a pumping voltage generator 240, disposing the oscillation signal generator 230 closer to the pumping voltage generator 240 than the reference oscillation signal generator 220 may decrease the total length of the signal lines if the positions of the reference oscillation signal generator 220 and the pumping voltage generator 240 are fixed.
On the other hand, when the constituent elements are disposed as described above, the signal line of the pre-charge signal OSCP_PCGENB becomes long, and thus, the time for transferring the enabled pre-charge signal OSCP_PCGENB from the oscillation signal generator 230 to the reference oscillation signal generator 220 is delayed as much as the length of the signal line of the pre-charge signal OSCP_PCGENB. Herein, if the delay time exceeds the half cycle of the reference oscillation signal OSCP_PRE, as illustrated in FIG. 7, the oscillation signals OSC1 to OSC6 may toggle in the pre-charge mode. For example, when the enabled pre-charge signal OSCP_PCGENB is not applied to the reference oscillation signal generator 220 within the half cycle of the reference oscillation signal OSCP_PRE, the logic level of the reference oscillation signal OSCP_PRE becomes logic high, which is unintentional, and thus, both the first and second source oscillation signals OSC_ODD and OSC_EVEN may not be at the logic low level. As a result, the logic level of the pre-charge signal OSCP_PCGENB becomes logic high. Therefore, a pumping voltage generator 240 performs a charge pumping operation unexpectedly, and this decreases the operation reliability of the second pumping voltage generation circuit 200.